Minimizing Power Dissipation in Combinational Circuits During Test Application
نویسندگان
چکیده
Yield, Reliability and Power Supply considerations motivate the need to minimize power dissipation during test application. Two techniques for minimizing power dissipation when tests are applied to static CMOS combinational circuits are proposed. They are: (i) Test set ordering; and (ii) Repetition of test vectors. We show that: although (i) is NP-Hard good heuristics can be developed; and an optimal polynomial time algorithm exists for (ii). Experimental evaluation of these algorithms show that considerable improvement in power dissipation can be achieved using these techniques.
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